per cell charge controller

No apologies needed! I understand readers are not putting in the intensity of effort trying to parse my wording that I am putting in trying to write clearly.

> Perhaps this is possible, but I do have some concerns with regards to how this will be done, which for now I'll keep to myself unless invited to engage.

Well "the What" now being clear, "the How" is all that's left, and so of course, do please share any of your concerns.

> isn't the point of the exercise to get all cells to the same (high, fully charged) voltage?

Yes, perhaps not ever as high as you would consider Full, my definition of that for daily cycling is well below 3.5Vpc, and prior to being put into storage, perhaps SoC of 30-40% whatever At Rest voltage that turns out to be

but in all cases, certainly all cells ending up as close as possible to the same At Rest finish voltage, without using any CV / Absorb charge stage, CC only, "to a voltage and disconnect" each cell independently.

> The problem, if I'm understanding correctly, is if some cells are nearly empty and others nearly full, it may be possible for a parallel connection to allow a discharging full cell to charge an empty cell at a too-high rate (absent some sort of cell-level current limiting)?

No, that may sometimes be an issue, but not the immediate one to be dealt with. For now we can assume most cells are usually pretty close. The goal is as above, to get them precisely to the same restingV, as least as close as possible using this methodology.

> My understanding is in assembling a bank of cells, you would normally charge each cell individually to a set top voltage.

Yes, normally, although many prefer bottom balancing, if they anticipate getting dangerously close to single-digit SoC levels.

However, in this project, the goal is for all the cells to get balanced every time, through this (here normal) independent-cell charging process. Eliminating the need for manual cell balancing or even checking / monitoring individual cell voltages, neither "live", nor as a periodic maintenance routine.

> The roughly equally charged individual cells would then be assembled in parallel for the desired AH capacity, essentially making one big cell in which small intercell variances will even out in a matter of minutes. A number of paralleled cells are then connected in series for desired bank voltage.

Again yes conventionally that disassembly / assembly process is a relatively infrequent event. Here it happens every charge cycle. But it would be derailing to the main topic of this thread to discuss that aspect, even if I knew how to do so.

So for purpose of this discussion, it's not a paralleled nor series'd pack, not assembled in any given xPyS arrangement, just a collection of individual cells, each being independently charged, through the single pair of wires and the relay in between

(dis)connecting each cell separately to/from the buss, no other gadgets or connections while charging, otherwise each cell isolated, standalone.

Clear?

> A little resistance will limit current flow. Say the maximum voltage difference ever possible is 1V. A .1 ohm resistor with limit this to 10A. But at 10mv difference, the current will drop to .1A

I do not if possible want anything slowing down getting to the finish point in normal operations.

I think it will not be that hard to get the central logic controller to put per-cell current-checking in place for temp / safety purposes.

So far IMO the best approach is just reducing the available-from-upstream current level to the buss in proportion to the count of currently closed relays / connected cells.

I've come across data that is leading me to be a bit more conservative, maybe .3-.6C at least for normal charge cycles, rather than allowing higher rates.

But the ability to allow up to .8-1C for rare cycles where a fast charge is required, would be nice.

But for now I want to focus on the core function, identifying components for the central controller, the relay functionality and sensing voltage accurately.