solar cell conductors

Re: solar cell conductors

Coming from micro-electronics and integrated circuits industry I find the metalization process used for PV cells as 'crude'. But in the PV cell industry, cost rules.

Thick film screen printed paste has binders that greatly increase its resistance. A printed silver based ink, once fired, is no where the same resistance and an equivalent pure silver runner. Silver also has a terrible electro-migration problem that requires a good sealer.

When using thick film screen printing it is important to have a flat surface. This is one reason I prefer mono-crystaline cells over poly-crystaline cell. Many times mono-crystaline wafers are rejects from the I.C. industry so are usually better quality then any polycrystaline substrate. We won't even mention amorphic cell.

I.C. industry uses thin film process which is vacuum deposition and electroplating. Vacuum deposition is just way too expensive for PV cells. The article mentions an improvement that uses a screen printed base metal that is electro-plated up with pure metal. This process eliminates the vacuum deposit but still gives low resistance runners. The weak link resistance wise is the base screen print contact to the wafer.

As to the capillary distribution, the trade off is total metal area blocking the sun, distance between the pickup metal and the surrounding higher resistance silicon area the current must travel to get to the metalization, and the resistance of metalization. Fine, low reistance metal runner closely spaced would be the best for low net PV series resistance, but there is a point of diminishing return. A good quality silicon PV cell produces about 35 mA/sq cm. so the collection metal distribution requirement is weighed against that current density.

If you want to get blown away look into the copper process used on latest sub-micron IC production. Trenches are etched in silicon oxide layer (glass insulation). The entire wafer has a base metal vacuum deposition followed by a copper electro-plating across the entire surface of the wafer. A mechanical fine grinder then polished off the copper surface until it gets down to where the oxide troughs were etched leaving just the very very fine copper runners in the troughs. This process is repeated up to six times for multi-layer metal interconnects. A 12 inch wafer of sub-micron geometry microcontroller I.C.'s run between $1500 and $3000 wholesale cost per wafer depending on the number of circuit processing layers. Not exactly in the ballpark of a typical PV cell.